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MCP14E3/MCP14E4/MCP14E5
TABLE 4-1:
ENABLE PIN LOGIC
MCP14E3
MCP14E4
MCP14E5
ENB_A
H
H
H
H
L
ENB_B
H
H
H
H
L
IN A
H
H
L
L
X
IN B
H
L
H
L
X
OUT A
L
L
H
H
L
OUT B
L
H
L
H
L
OUT A
H
H
L
L
L
OUT B
H
L
H
L
L
OUT A
L
L
H
H
L
OUT B
H
L
H
L
L
Placing a ground plane beneath the MCP14E3/
5V
MCP14E4/MCP14E5 will help as a radiated noise
shield as well as providing some heat sinking for power
dissipated within the device.
ENB_x
V EN_H
V EN_L
4.6
Power Dissipation
0V
The total internal power dissipation in a MOSFET driver
is the summation of three separate power dissipation
t D3
t D4
elements.
V DD
EQUATION 4-1:
OUT x
90%
Where:
P T = P L + P Q + P CC
0V
FIGURE 4-3:
10%
Enable Timing Waveform.
P T
P L
P Q
P CC
=
=
=
=
Total power dissipation
Load power dissipation
Quiescent power dissipation
Operating power dissipation
4.4
Decoupling Capacitors
4.6.1
CAPACITIVE LOAD DISSIPATION
Careful layout and decoupling capacitors are highly
recommended when using MOSFET drivers. Large
currents are required to charge and discharge
capacitive loads quickly. For example, 2.5A are needed
to charge a 2200 pF load with 18V in 16 ns.
The power dissipation caused by a capacitive load is a
direct function of frequency, total capacitive load, and
supply voltage. The power lost in the MOSFET driver
for a complete charging and discharging cycle of a
MOSFET is:
To operate the MOSFET driver over a wide frequency
range with low supply impedance, a ceramic and low
ESR film capacitor are recommended to be placed in
parallel between the driver V DD and GND. A 1.0 μF low
ESR film capacitor and a 0.1 μF ceramic capacitor
EQUATION 4-2:
P L = f × C T × V DD
Where:
2
should be used. These capacitors should be placed
close to the driver to minimized circuit board parasitics
and provide a local source for the required current.
f
C T
=
=
Switching frequency
Total load capacitance
4.5
PCB Layout Considerations
V DD
=
MOSFET driver supply voltage
Proper PCB layout is important in a high current, fast
switching circuit to provide proper device operation and
robustness of design. PCB trace loop area and
inductance should be minimized by the use of ground
planes or trace under MOSFET gate drive signals,
separate analog and power grounds, and local driver
decoupling.
? 2008 Microchip Technology Inc.
DS22062B-page 13
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